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eol data sheet ?2007 silicon storage technology, inc. s71146-07-eol 6/07 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. mpf is a trademark of silicon storage technology, inc. these specifications are subject to change without notice. 8 mbit (x8) multi-purpose flash sst39lf080 / sst39vf080 features: ? organized as 1m x8 ? single voltage read and write operations ? 3.0-3.6v for sst39lf080 ? 2.7-3.6v for sst39vf080 ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? low power consumption (typical values at 14 mhz) ? active current: 12 ma (typical) ? standby current: 4 a (typical) ? auto low power mode: 4 a (typical) ? sector-erase capability ? uniform 4 kbyte sectors ? block-erase capability ? uniform 64 kbyte blocks ? fast read access time: ? 55 ns for sst39lf080 ? 70 and 90 ns for sst39vf080 ? latched address and data ? fast erase and byte-program: ? sector-erase time: 18 ms (typical) ? block-erase time: 18 ms (typical) ? chip-erase time: 70 ms (typical) ? byte-program time: 14 s (typical) ? chip rewrite time: 15 seconds (typical) for sst39lf/vf080 ? automatic write timing ? internal v pp generation ? end-of-write detection ? toggle bit ? data# polling ? cmos i/o compatibility ? jedec standard ? flash eeprom pinouts and command sets ? packages available ? 40-lead tsop (10mm x 20mm) ? 48-ball tfbga (6mm x 8mm) product description the sst39lf/vf080 devices are 1m x8 cmos multi-pur- pose flash (mpf) manufactured with sst?s proprietary, high-performance cmos superflash technology. the split-gate cell design and thick-oxide tunneling injector attain better reliability and ma nufacturability compared with alternate approaches. the sst39lf080 write (program or erase) with a 3.0-3.6v power supply. the sst39vf080 write (program or erase) with a 2.7-3.6v power supply. they conform to jedec standard pinouts for x8 memories. featuring high performance byte-program, the sst39lf/ vf080 devices provide a typical byte-program time of 14 sec. the devices use toggle bit or data# polling to indi- cate the completion of program operation. to protect against inadvertent write, they have on-chip hardware and software data protection schemes. designed, manufac- tured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endurance of 10,000 cycles. data retention is rated at greater than 100 years. the sst39lf/vf080 devices are suited for applications that require convenient and economical updating of pro- gram, configuration, or data memory. for all system appli- cations, they significantly improve performance and reliability, while lowering power consumption. they inher- ently use less energy during erase and program than alter- native flash technologies. the total energy consumed is a function of the applied voltage, current, and time of applica- tion. since for any given voltage range, the superflash technology uses less current to program and has a shorter erase time, the total energy consumed during any erase or program operation is less than alternative flash technolo- gies. they also improve flexibility while lowering the cost for program, data, and configuration storage applications. the superflash technology provides fixed erase and pro- gram times, independent of the number of erase/program cycles that have occurred. therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/pro- gram cycles. to meet high density, surface mount requirements, the sst39lf/vf080 are offered in 40-lead tsop and 48- ball tfbga packages. see figures 1 and 2 for pin assignments. sst39lf/vf0803.0 & 2.7v 8mb (x8) mpf memories
2 eol data sheet 8 mbit multi-purpose flash sst39lf080 / sst39vf080 ?2007 silicon storage technology, inc. s71146-07-eol 6/07 device operation commands are used to initiate the memory operation func- tions of the device. commands are written to the device using standard microprocessor write sequences. a com- mand is written by asserting we# low while keeping ce# low. the address bus is latc hed on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. the sst39lf/vf080 also have the auto low power mode which puts the device in a near standby mode after data has been accessed with a valid read operation. this reduces the i dd active read current from typically 15 ma to typically 4 a. the auto low power mode reduces the typi- cal i dd active read current to the range of 1 ma/mhz of read cycle time. the device exits the auto low power mode with any address transition or control signal transition used to initiate another read cycle, with no access time penalty. note that the device does not enter auto low power mode after power-up with ce# held steadily low until the first address transition or ce# is driven high. read the read operation of the sst39lf/vf080 is controlled by ce# and oe#, both have to be low for the system to obtain data from the outputs. ce# is used for device selec- tion. when ce# is high, t he chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce# or oe# is high. refer to the read cycle timing diagram for further details (figure 3). byte-program operation the sst39lf/vf080 are programmed on a byte-by-byte basis. before programming, the sector where the byte exists must be fully erased. the program operation is accomplished in three steps. the first step is the three-byte load sequence for software data protection. the second step is to load byte address and byte data. during the byte- program operation, the addresses are latched on the falling edge of either ce# or we#, whichever occurs last. the data is latched on the rising edge of either ce# or we#, whichever occurs first. the third step is the internal pro- gram operation which is initiated after the rising edge of the fourth we# or ce#, whichever occurs first. the program operation, once initiated, will be completed within 20 s. see figures 4 and 5 for we# and ce# controlled program operation timing diagrams and figure 16 for flowcharts. during the program operation, the only valid reads are data# polling and toggle bit. during the internal program operation, the host is free to perform additional tasks. any commands issued during the internal program operation are ignored. sector/block-e rase operation the sector- (or block-) erase operation allows the system to erase the device on a sector-by-sector (or block-by- block) basis. the sst39lf/vf080 offer both sector-erase and block-erase mode. the sector architecture is based on uniform sector size of 4 kbyte. the block-erase mode is based on uniform block size of 64 kbyte. the sector- erase operation is initiated by executing a six-byte com- mand sequence with sector-erase command (30h) and sector address (sa) in the last bus cycle. the block-erase operation is initiated by executing a six-byte command sequence with block-erase command (50h) and block address (ba) in the last bus cycle. the sector or block address is latched on the falling edge of the sixth we# pulse, while the command (30h or 50h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. the end-of- erase operation can be determined using either data# polling or toggle bit methods. see figures 9 and 10 for tim- ing waveforms. any commands issued during the sector- or block-erase operation are ignored. chip-erase operation the sst39lf/vf080 provide a chip-erase operation, which allows the user to erase the entire memory array to the ?1? state. this is useful when the entire device must be quickly erased. the chip-erase operation is initiated by executing a six- byte command sequence with chip-erase command (10h) at address 5555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. during the erase operation, the only valid read is toggle bit or data# polling. see table 4 for the command sequence, figure 8 for timing diagram, and figure 19 for the flowchart. any commands issued dur- ing the chip-erase operation are ignored. write operation status detection the sst39lf/vf080 provide two software means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the software detection includes two status bits: data# polling (dq 7 ) and toggle bit (dq 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which initiates the internal program or erase operation.
eol data sheet 8 mbit multi-purpose flash sst39lf080 / sst39vf080 3 ?2007 silicon storage technology, inc. s71146-07-eol 6/07 the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to con- flict with either dq 7 or dq 6 . in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejec- tion is valid. data# polling (dq 7 ) when the sst39lf/vf080 are in the internal program operation, any attempt to read dq 7 will produce the com- plement of the true data. once the program operation is completed, dq 7 will produce true data. note that even though dq 7 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive read cycles after an interval of 1 s. during internal erase opera- tion, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector-, block- or chip-erase, the data# polling is valid after the ris- ing edge of sixth we# (or ce#) pulse. see figure 6 for data# polling timing diagram and figure 17 for a flowchart. toggle bit (dq 6 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. when the internal program or erase operation is completed, the dq 6 bit will stop toggling. the device is then ready for the next opera- tion. the toggle bit is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector-, block-, or chip-erase, the toggle bit is valid after the rising edge of sixth we# (or ce#) pulse. see figure 7 for toggle bit timing diagram and figure 17 for a flowchart. data protection the sst39lf/vf080 provide both hardware and soft- ware features to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection: a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection: the write operation is inhibited when v dd is less than 1.5v. write inhibit mode: forcing oe# low, ce# high, or we# high will inhibit the write oper ation. this prevents inadvert- ent writes during power-up or power-down. software data protection (sdp) the sst39lf/vf080 provide the jedec approved soft- ware data protection scheme for all data alteration opera- tions, i.e., program and erase. any program operation requires the inclusion of the three-byte sequence. the three-byte load sequence is used to initiate the program operation, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of six-byte sequence. the sst39lf/vf080 devices are shipped with the software data protection permanently enabled. see table 4 for the specific software command codes. during sdp command sequence, invalid com- mands will abort the device to read mode within t rc. common flash memory interface (cfi) the sst39lf/vf080 also contain the cfi information to describe the characteristics of the device. in order to enter the cfi query mode, the system must load the three-byte sequence, similar to the software id entry command. the last byte cycle of this command loads 98h (cfi query command) to address 5555h. once the device enters the cfi query mode, the system can read cfi data at the addresses given in tables 5 through 7. the system must write the cfi exit command to return to read mode from the cfi query mode.
4 eol data sheet 8 mbit multi-purpose flash sst39lf080 / sst39vf080 ?2007 silicon storage technology, inc. s71146-07-eol 6/07 product identification the product identification mode identifies the device as sst39lf080 or sst39vf080 and manufacturer as sst. this mode may be accessed by software operations. users may use the software product identification opera- tion to identify the part (i.e., using the device id) when using multiple manufacturers in the same socket. for details, see table 4 for software operation, figure 11 for the software id entry and read timing diagram and figure 18 for the software id entry command sequence flowchart. product identification mode exit/ cfi mode exit in order to return to the standard read mode, the software product identification mode must be exited. exit is accom- plished by issuing the software id exit command sequence, which returns the device to the read operation. this command may also be used to reset the device to the read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. please note that the software id exit/ cfi exit command is ignored during an internal program or erase operation. see table 4 for software command codes, figure 13 for timing waveform and figure 18 for a flowchart. table 1: p roduct i dentification address data manufacturer?s id 0000h bfh device id sst39lf/vf080 0001h d8h t1.3 1146 y-decoder i/o buffers and data latches 1146 b1.2 address buffer & latches x-decoder dq 7 - dq 0 memory address oe# ce# we# superflash memory control logic f unctional b lock d iagram
eol data sheet 8 mbit multi-purpose flash sst39lf080 / sst39vf080 5 ?2007 silicon storage technology, inc. s71146-07-eol 6/07 figure 1: pin assignments for 40-lead tsop figure 2: pin assignments for 48-ball tfbga a16 a15 a14 a13 a12 a11 a9 a8 we# nc nc nc a18 a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a17 v ss nc a19 a10 dq7 dq6 dq5 dq4 v dd v dd nc dq3 dq2 dq1 dq0 oe# v ss ce# a0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1146 f01.3 standard pinout top view die up a14 a9 we# nc a7 a3 a13 a8 nc nc a18 a4 a15 a11 nc nc a6 a2 a16 a12 nc nc a5 a1 a17 a19 dq5 dq2 dq0 a0 nc a10 nc dq3 nc ce# nc dq6 v dd v dd nc oe# v ss dq7 dq4 nc dq1 v ss 1146 48-tfbga p2.2 top view (balls facing down) 6 5 4 3 2 1 a b c d e f g h
6 eol data sheet 8 mbit multi-purpose flash sst39lf080 / sst39vf080 ?2007 silicon storage technology, inc. s71146-07-eol 6/07 table 2: p in d escription symbol pin name functions a ms 1 -a 0 address inputs to provide memory addresses. during sector-erase a ms -a 12 address lines will select the sector. during block-erase a ms -a 16 address lines will select the block. dq 7 -dq 0 data input/output to ou tput data during read cycles and receive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-state when oe# or ce# is high. ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers. we# write enable to control the write operations. v dd power supply to provide power s upply voltage: 3.0-3.6v for sst39lf080 2.7-3.6v for sst39vf080 v ss ground nc no connection unconnected pins. t2.4 1146 1. a ms = most significant address a ms = a 19 for sst39lf/vf080 table 3: o peration m odes s election mode ce# oe# we# dq address read v il v il v ih d out a in program v il v ih v il d in a in erase v il v ih v il x 1 1. x can be v il or v ih , but no other value. sector or block address, xxh for chip-erase standby v ih x x high z x write inhibit x v il x high z/ d out x xxv ih high z/ d out x product identification software mode v il v il v ih see table 4 t3.4 1146
eol data sheet 8 mbit multi-purpose flash sst39lf080 / sst39vf080 7 ?2007 silicon storage technology, inc. s71146-07-eol 6/07 table 4: s oftware c ommand s equence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 data addr 1 data addr 1 data addr 1 data addr 1 data addr 1 data byte-program 5555h aah 2aaah 55h 5555h a0h wa 2 data sector-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa x 3 30h block-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h ba x 3 50h chip-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h software id entry 4,5 5555h aah 2aaah 55h 5555h 90h cfi query entry 4 5555h aah 2aaah 55h 5555h 98h software id exit 6 / cfi exit xxh f0h software id exit 6 / cfi exit 5555h aah 2aaah 55h 5555h f0h t4.4 1146 1. address format a 14 -a 0 (hex), addresses a 19 -a 15 can be v il or v ih , but no other value, for the command sequence for sst39lf/vf080. 2. wa = program byte address 3. sa x for sector-erase; uses a ms -a 12 address lines ba x for block-erase; uses a ms -a 16 address lines a ms = most significant address a ms = a 19 for sst39lf/vf080 4. the device does not remain in software product id mode if powered down. 5. with a ms -a 1 = 0; sst manufacturer?s id = bfh, is read with a 0 = 0 sst39lf/vf080 device id = d8h, is read with a 0 = 1 6. both software id exit operations are equivalent table 5: cfi q uery i dentification s tring 1 for sst39lf/vf080 1. refer to cfi publication 100 for more details. address data data 10h 51h query unique ascii string ?qry? 11h 52h 12h 59h 13h 01h primary oem command set 14h 07h 15h 00h address for primary extended table 16h 00h 17h 00h alternate oem command set (00h = none exists) 18h 00h 19h 00h address for alternate oem extended table (00h = none exits) 1ah 00h t5.4 1146
8 eol data sheet 8 mbit multi-purpose flash sst39lf080 / sst39vf080 ?2007 silicon storage technology, inc. s71146-07-eol 6/07 table 6: s ystem i nterface i nformation for sst39lf/vf080 address data data 1bh 27h 1 v dd min (program/erase) 30h 1 dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1ch 36h v dd max (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1dh 00h v pp min (00h = no v pp pin) 1eh 00h v pp max (00h = no v pp pin) 1fh 04h typical time out for byte-program 2 n s (2 4 = 16 s) 20h 00h typical time out for min size buffer program 2 n s (00h = not supported) 21h 04h typical time out for individual sector/block-erase 2 n ms (2 4 = 16 ms) 22h 06h typical time out for chip-erase 2 n ms (2 6 = 64 ms) 23h 01h maximum time out for byte-program 2 n times typical (2 1 x 2 4 = 32 s) 24h 00h maximum time out for buffer program 2 n times typical 25h 01h maximum time out for individual sector/block-erase 2 n times typical (2 1 x 2 4 = 32 ms) 26h 01h maximum time out for chip-erase 2 n times typical (2 1 x 2 6 = 128 ms) t6.2 1146 1. 0030h for sst39lf080 and 0027h for sst39vf080 table 7: d evice g eometry i nformation for sst39lf/vf080 address data data 27h 14h device size = 2 n bytes (14h = 20; 2 20 = 1 mbyte) 28h 00h flash device interface description; 0000h = x8-only asynchronous interface 29h 00h 2ah 00h maximum number of bytes in multi-byte write = 2 n (00h = not supported) 2bh 00h 2ch 02h number of erase sector/block sizes supported by device 2dh ffh sector information (y + 1 = number of sectors; z x 256b = sector size) 2eh 00h y = 255 + 1 = 256 sectors (00ffh = 255) 2fh 10h 30h 00h z = 16 x 256 bytes = 4 kbyte/sector (0010h = 16) 31h 0fh block information (y + 1 = number of blocks; z x 256b = block size) 32h 00h y = 15 + 1 = 16 blocks (000fh = 15) 33h 00h 34h 01h z = 256 x 256 bytes = 64 kbyte/block (0100h = 256) t7.0 1146
eol data sheet 8 mbit multi-purpose flash sst39lf080 / sst39vf080 9 ?2007 silicon storage technology, inc. s71146-07-eol 6/07 absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. exposu re to absolute maximum stress rating co nditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v voltage on a 9 pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 13.2v package power dissipation capability (ta = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount lead soldering temperature (3 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240c output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. outputs shorted for no more than one second. no more than one output shorted at a time. o perating r ange for sst39lf080 range ambient temp v dd commercial 0c to +70c 3.0-3.6v o perating r ange for sst39vf080 range ambient temp v dd commercial 0c to +70c 2.7-3.6v industrial -40c to +85c 2.7-3.6v ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . c l = 30 pf for sst39lf080 output load . . . . . . . . . . . . . . . . . . . . c l = 100 pf for sst39vf080 see figures 14 and 15
10 eol data sheet 8 mbit multi-purpose flash sst39lf080 / sst39vf080 ?2007 silicon storage technology, inc. s71146-07-eol 6/07 table 8: dc o perating c haracteristics v dd = 3.0-3.6v for sst39lf080 and 2.7-3.6v for sst39vf080 1 symbol parameter limits test conditions min max units i dd power supply current address input=v ilt /v iht , at f=1/t rc min v dd =v dd max read 2 20 ma ce#=v il , oe#=we#=v ih , all i/os open program and erase 30 ma ce#=we#=v il , oe#=v ih i sb standby v dd current 20 a ce#=v ihc , v dd =v dd max i alp auto low power 20 a ce#=v ilc , v dd =v dd max all inputs=v ss or v dd, we#=v ihc i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v v dd =v dd min v ilc input low voltage (cmos) 0.3 v v dd =v dd max v ih input high voltage 0.7v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v ol output low voltage 0.2 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min t8.7 1146 1. typical conditions for the active current shown on the front data sheet page are average values at 25c (room temperature), and v dd = 3v for vf devices. not 100% tested. 2. values are for 70 ns conditions. see the multi-purpose flash power rating application note for further information. table 9: r ecommended s ystem p ower - up t imings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. power-up to read operation 100 s t pu-write 1 power-up to program/erase operation 100 s t9.1 1146 table 10: c apacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t10.0 1146 table 11: r eliability c haracteristics symbol parameter minimum specification units test method n end 1,2 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. 2. n end endurance rating is qualified as a 10,000 cycl e minimum for the whole device. a sector- or block-level rating would result in a higher minimum specification. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t11.2 1146
eol data sheet 8 mbit multi-purpose flash sst39lf080 / sst39vf080 11 ?2007 silicon storage technology, inc. s71146-07-eol 6/07 ac characteristics table 12: r ead c ycle t iming p arameters v dd = 3.0-3.6v for sst39lf080 and 2.7-3.6v for sst39vf080 symbol parameter sst39lf080-55 sst39vf080-70 sst39vf080-90 units min max min max min max t rc read cycle time 55 70 90 ns t ce chip enable access time 55 70 90 ns t aa address access time 55 70 90 ns t oe output enable access time 30 35 45 ns t clz 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. ce# low to active output 0 0 0 ns t olz 1 oe# low to active output 0 0 0 ns t chz 1 ce# high to high-z output 15 20 30 ns t ohz 1 oe# high to high-z output 15 20 30 ns t oh 1 output hold from address change 0 0 0 ns t12.4 1146 table 13: p rogram /e rase c ycle t iming p arameters symbol parameter min max units t bp byte-program time 20 s t as address setup time 0 ns t ah address hold time 30 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp ce# pulse width 40 ns t wp we# pulse width 40 ns t wph 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. we# pulse width high 30 ns t cph 1 ce# pulse width high 30 ns t ds data setup time 30 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t se sector-erase 25 ms t be block-erase 25 ms t sce chip-erase 100 ms t13.0 1146
12 eol data sheet 8 mbit multi-purpose flash sst39lf080 / sst39vf080 ?2007 silicon storage technology, inc. s71146-07-eol 6/07 figure 3: read cycle timing diagram figure 4: we# controlled program cycle timing diagram 1146 f02.2 address a ms-0 dq 7-0 we# oe# ce# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz 1146 f03.2 address a ms-0 dq 7-0 t dh t wph t ds t wp t ah t as t ch t cs ce# sw0 sw1 sw2 5555 2aaa 5555 addr aa 55 a0 data internal program operation starts byte (addr/data) oe# we# t bp
eol data sheet 8 mbit multi-purpose flash sst39lf080 / sst39vf080 13 ?2007 silicon storage technology, inc. s71146-07-eol 6/07 figure 5: ce# controlled prog ram cycle timing diagram figure 6: data# polling timing diagram 1146 f04.2 address a ms-0 dq 7-0 t dh t cph t ds t cp t ah t as t ch t cs we# sw0 sw1 sw2 5555 2aaa 5555 addr aa 55 a0 data internal program operation starts byte (addr/data) oe# ce# t bp 1146 f05.2 address a ms-0 dq 7 data data# data# data we# oe# ce# t oeh t oe t ce t oes
14 eol data sheet 8 mbit multi-purpose flash sst39lf080 / sst39vf080 ?2007 silicon storage technology, inc. s71146-07-eol 6/07 figure 7: toggle bit timing diagram figure 8: we# controlled chip-erase timing diagram 1146 f06.2 address a ms-0 dq 6 we# oe# ce# t oe t oeh t ce t oes two read cycles with same outputs 1146 f08.3 address a ms-0 dq 7-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 10 55 aa 80 aa 5555 oe# ce# six-byte code for chip-erase t sce t wp
eol data sheet 8 mbit multi-purpose flash sst39lf080 / sst39vf080 15 ?2007 silicon storage technology, inc. s71146-07-eol 6/07 figure 9: we# controlled block-erase timing diagram figure 10: we# controlled sector-erase timing diagram 1146 f09.3 address a ms-0 dq 7-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 50 55 aa 80 aa ba x oe# ce# six-byte code for block-erase t be t wp 1146 f10.3 address a ms-0 dq 7-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 55 30 55 aa 80 aa sa x oe# ce# t se t wp six-byte code for sector-erase
16 eol data sheet 8 mbit multi-purpose flash sst39lf080 / sst39vf080 ?2007 silicon storage technology, inc. s71146-07-eol 6/07 figure 11: software id entry and read figure 12: cfi query entry and read note: device id = d8h for sst39lf/vf080 1146 f11.4 address a 14-0 t ida dq 7-0 we# sw0 sw1 sw2 5555 2aaa 5555 0000 0001 three-byte sequence for software id entry t wp t wph t aa bf device id 55 aa 90 oe# ce# 1146 f12.0 address a 14-0 t ida dq 7-0 we# sw0 sw1 sw2 5555 2aaa 5555 oe# ce# three-byte sequence for cfi query entry t wp t wph t aa 55 aa 98
eol data sheet 8 mbit multi-purpose flash sst39lf080 / sst39vf080 17 ?2007 silicon storage technology, inc. s71146-07-eol 6/07 figure 13: software id exit/cfi exit 1146 f13.0 address a 14-0 dq 7-0 t ida t wp t whp we# sw0 sw1 sw2 5555 2aaa 5555 three-byte sequence for software id exit and reset oe# ce# aa 55 f0
18 eol data sheet 8 mbit multi-purpose flash sst39lf080 / sst39vf080 ?2007 silicon storage technology, inc. s71146-07-eol 6/07 figure 14: ac input/output reference waveforms figure 15: a test load example 1146 f14.1 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 1146 f15.1 to tester to dut c l
eol data sheet 8 mbit multi-purpose flash sst39lf080 / sst39vf080 19 ?2007 silicon storage technology, inc. s71146-07-eol 6/07 figure 16: byte-program algorithm 1146 f16.1 start load data: aah address: 5555h load data: 55h address: 2aaah load data: a0h address: 5555h load byte address/byte data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed
20 eol data sheet 8 mbit multi-purpose flash sst39lf080 / sst39vf080 ?2007 silicon storage technology, inc. s71146-07-eol 6/07 figure 17: wait options 1146 f17.0 wait t bp , t sce, t se or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same byte data# polling program/erase completed program/erase completed read byte is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated
eol data sheet 8 mbit multi-purpose flash sst39lf080 / sst39vf080 21 ?2007 silicon storage technology, inc. s71146-07-eol 6/07 figure 18: software id/cfi command flowcharts 1146 f18.1 load data: aah address: 5555h software product id entry command sequence load data: 55h address: 2aaah load data: 90h address: 5555h wait t ida read software id load data: aah address: 5555h cfi query entry command sequence load data: 55h address: 2aaah load data: 98h address: 5555h wait t ida read cfi data load data: aah address: 5555h software id exit/cfi exit command sequence load data: 55h address: 2aaah load data: f0h address: 5555h load data: f0h address: xxh return to normal operation wait t ida wait t ida return to normal operation
22 eol data sheet 8 mbit multi-purpose flash sst39lf080 / sst39vf080 ?2007 silicon storage technology, inc. s71146-07-eol 6/07 figure 19: erase command sequence 1146 f19.1 load data: aah address: 5555h chip-erase command sequence load data: 55h address: 2aaah load data: 80h address: 5555h load data: 55h address: 2aaah load data: 10h address: 5555h load data: aah address: 5555h wait t sce chip erased to ffh load data: aah address: 5555h sector-erase command sequence load data: 55h address: 2aaah load data: 80h address: 5555h load data: 55h address: 2aaah load data: 30h address: sa x load data: aah address: 5555h wait t se sector erased to ffh load data: aah address: 5555h block-erase command sequence load data: 55h address: 2aaah load data: 80h address: 5555h load data: 55h address: 2aaah load data: 50h address: ba x load data: aah address: 5555h wait t be block erased to ffh
eol data sheet 8 mbit multi-purpose flash sst39lf080 / sst39vf080 23 ?2007 silicon storage technology, inc. s71146-07-eol 6/07 product ordering information valid combinations for sst39lf080 sst39lf080-55-4c-ei sst39lf080-55-4c-b3k sst39lf080-55-4c-eie sst39lf080-55-4c-b3ke valid combinations for sst39vf080 sst39vf080-70-4c-ei sst39vf080-70-4c-b3k SST39VF080-70-4C-EIE sst39vf080-70-4c-b3ke sst39vf080-90-4c-ei sst39vf080-90-4c-b3k sst39vf080-90-4c-eie sst39vf080-90-4c-b3ke sst39vf080-70-4i-ei sst39vf080-70-4i-b3k sst39vf080-70-4i-eie sst39vf080-70-4i-b3ke sst39vf080-90-4i-ei sst39vf080-90-4i-b3k sst39vf080-90-4i-eie sst39vf080-90-4i-b3ke note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. environmental attribute e = non-pb package modifier i = 40 leads k = 48 balls package type b3 = tfbga (0.8mm pitch, 6mm x 8mm) e = tsop (type 1, die up, 10mm x 20mm) temperature range c = commercial = 0c to +70c i = industrial = -40c to +85c minimum endurance 4 = 10,000 cycles read access speed 55 = 55 ns 70 = 70 ns 90 = 90 ns device density 080 = 8 mbit voltag e l = 3.0-3.6v v = 2.7-3.6v product series 39 = multi-purpose flash sst 39 vf 080 - 70 - 4c - b3k e xx x x xxxx - xxx -xx - xxx x
24 eol data sheet 8 mbit multi-purpose flash sst39lf080 / sst39vf080 ?2007 silicon storage technology, inc. s71146-07-eol 6/07 packaging diagrams figure 20: 40-lead thin small outline package (tsop) 10mm x 20mm sst package code: ei 18.50 18.30 20.20 19.80 0.70 0.50 10.10 9.90 0.27 0.17 1.05 0.95 0.15 0.05 0.70 0.50 40-tsop-ei-7 note: 1. complies with jedec publication 95 mo-142 cd dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. pin # 1 identifier 0.50 bsc 1.20 max. 0?- 5? detail 1mm
eol data sheet 8 mbit multi-purpose flash sst39lf080 / sst39vf080 25 ?2007 silicon storage technology, inc. s71146-07-eol 6/07 figure 21: 48-ball thin-profile, fine-pitch ball grid array (tfbga) 6mm x 8mm sst package code: b3k table 14: r evision h istory number description date 03 ? 2002 data book may 2002 04 ? b3k package no longer offered for sst39lf/vf016 ? part number changes - see page 23 for additional information ? changes to table 8 on page 10 ? added footnote for mpf power usage and typical conditions ? changed the i alp test onditions ? clarified the test conditions for power supply current and read parameters ? corrected the i dd read current from 15 ma to 20 ma ? corrected the i dd program and erase current from 20 ma to 30 ma mar 2003 05 ? removed 16 mbit parts (sst39lf/vf016); refer to sst39vf1681/1682 (s71243) aug 2003 06 ? 2004 data book ? updated b3k package diagram nov 2003 07 ? end of life data sheet for all devices in s71146 june 2007 a1 corner h g f e d c b a a b c d e f g h bottom view top view side view 6 5 4 3 2 1 6 5 4 3 2 1 seating plane 0.35 0.05 1.10 0.10 0.12 6.00 0.20 0.45 0.05 (48x) a1 corner 8.00 0.20 0.80 4.00 0.80 5.60 48-tfbga-b3k-6x8-450mic-4 note: 1. complies with jedec publication 95, mo-210, variant 'ab-1', although some dimensions may be more stringent. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size is 0.38 mm ( 0.05 mm) 1mm silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com

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